MIRA

MIRA is a mathematical intermediate representation of an input program and the target architecture. It contains the typical program specific and architecture specific information required by different register allocators. A sample MIRA program looks like this.

A MIRA program consists of sets and parameters written in AMPL syntax. A set is a symbolic enumeration and a parameter can be a scalar value or a collection of values indexed by one or more sets.

The description for the MIRA language can be found in the technical report.

A short description of each term is given here for a quick reference:

• loadCost : Cost of a load instruction.
• loadPairCost : Cost of a load-pair instruction.
• invLoadCost : Cost of an inversion induced by a load-pair instruction.
• storeCost : Cost of a store instruction.
• storePairCost : Cost of a store-pair instruction.
• invStoreCost : Cost of an inversion induced by a store-pair instruction.
• nRegs : Number of registers in the target architecture.
• nInsts : Number of instructions/
• nLSMPseudos : Number of local scalar pseudos (non memory pseudos).
• nPseudos: Total number of pseudos.
• nMoves: Number of move instructions.
• pseudos: Set of pseudos.
• Loc: Set of locations for the pseudos. Only local scalar pseudos need locations.
• insts: This is the set of instructions. Note that, RALF doubles the number of instructions for ease of allocation. i.e. instruction number 0, and 1 correspond to instruction 0 in the program, instructions 2 and 3 correspond to instruction 1 in the program etc.
  
• regs: Set of registers.
  
• callerSave: Caller save registers.
• freq: Frequency of execution of each instruction.
• Live: Liveness information for the pseudos.
• LiveHardReg: Liveness information for the hard registers.
• basePseudoReg: Base pseudo register of a memory pseudo, if there is one.
• baseHardReg: Base hard register of a memory pseudo, if there is one.
• req: The "use" information of pseuods at each instruction.
• HRreq: The "use" information of registers at each instruction.
• prevInst: The control flow information within the instruction in one basic block.
• prevInsts: The control information between the instructions at the beginning and end of different basic blocks.
• def: The "def" information of pseudos at each instruction.
• defHardReg: The "def" information of registers at each instruction.
• lsmPseuods: Local scalar pseudos.
• memPseudos: Memory pseudos.
• nsEdge: Pairing information of memory pseudos.
• equiv: Equivalent pseudos (Currently unused).
• knownStores: A write to a memory pseudo.
• knownHardStore: A write a memory pseudo, with a machine register as base.
  
• knownLoads: A read from a memory pseudo.
• jumpInst: Jump instructions.
• callInst: Call instructions.
• Moves: Move instructions.