Target Data Layout
Debug Information
Module Pass Manager
  Function Pass Manager
    Immediate Dominators Construction (VMCore/Dominators.cpp)
    ET Forest Construction (VMCore/Dominators.cpp)
    Module Verifier
--  Module Verifier
    Natural Loop Construction (Analysis/LoopInfo.cpp)
    Dominator Set Construction (VMCore/Dominators.cpp)
    Dominator Tree Construction (VMCore/Dominators.cpp)
--  Immediate Dominators Construction (VMCore/Dominators.cpp)
1   Canonicalize natural loops (Transforms/Utils/LoopSimplify.cpp)
--  Dominator Set Construction (VMCore/Dominators.cpp)
--  Dominator Tree Construction (VMCore/Dominators.cpp)
2   Scalar Evolution Analysis (Analysis/ScalarEvolution.cpp)
3   Loop Strength Reduction (Transforms/Scalar/LoopStrengthReduce.cpp)
--  ET Forest Construction (VMCore/Dominators.cpp)
1-  Loop Strength Reduction (Transforms/Scalar/LoopStrengthReduce.cpp)
3-  Canonicalize natural loops (Transforms/Utils/LoopSimplify.cpp)
2-  Scalar Evolution Analysis (Analysis/ScalarEvolution.cpp)
--  Natural Loop Construction (Analysis/LoopInfo.cpp)
4    Lower GC intrinsics, for GCless code generators
                                       (Transforms/Scalar/LowerGC.cpp)
4-  Lower GC intrinsics, for GCless code generators
5   Lower invoke and unwind, for unwindless code generators
                                   (Transforms/Scalar/LowerInvoke.cpp)
5-  Lower invoke and unwind, for unwindless code generators
    Simplify the CFG (Transforms/Scalar/SimplifyCFG.cpp)
--  Simplify the CFG (Transforms/Scalar/SimplifyCFG.cpp)
    Remove unreachable blocks from the CFG
--  Remove unreachable blocks from the CFG
    Break critical edges in CFG
--  Break critical edges in CFG
    PowerPC DAG->DAG Pattern Instruction Selection
--  PowerPC DAG->DAG Pattern Instruction Selection
    Immediate Dominators Construction
    ET Forest Construction
--  Immediate Dominators Construction
    Natural Loop Construction
--  ET Forest Construction
    Virtual to def/use mapping - Fernando.
--  Natural Loop Construction
    Edge liveness analyses - Fernando.
    Register allocation via coloring of chordal graphs.
--  Register allocation via coloring of chordal graphs.
--  Virtual to def/use mapping - Fernando.
--  Edge liveness analyses - Fernando.
    Prolog/Epilog Insertion & Frame Finalization
--  Prolog/Epilog Insertion & Frame Finalization
    PowerPC Branch Selection
--  PowerPC Branch Selection
    Darwin PPC Assembly Printer
--  Darwin PPC Assembly Printer
    Machine Code Deleter
--  Machine Code Deleter