Pass Arguments:  -domtree -verify -loops -loopsimplify -scalar-evolution
-loop-reduce -lowergc -lowerinvoke -unreachableblockelim -codegenprepare
-phi-node-elimination -livevars
Target Data Layout
Basic Alias Analysis (default AA impl)
Module Information
  FunctionPass Manager
    Dominator Tree Construction
    Module Verifier
--    Module Verifier
    Natural Loop Construction
    Canonicalize natural loops
    Scalar Evolution Analysis
    Loop Pass Manager
      Loop Strength Reduction
--      Loop Strength Reduction
--    Target Data Layout
--    Dominator Tree Construction
--    Canonicalize natural loops
--    Natural Loop Construction
--    Scalar Evolution Analysis
    Lower GC intrinsics, for GCless code generators
--    Lower GC intrinsics, for GCless code generators
    Lower invoke and unwind, for unwindless code generators
--    Lower invoke and unwind, for unwindless code generators
    Remove unreachable blocks from the CFG
--    Remove unreachable blocks from the CFG
    Optimize for code generation
--    Optimize for code generation
    X86 DAG->DAG Instruction Selection
--    X86 DAG->DAG Instruction Selection
    Eliminate PHI nodes for register allocation
    Simple Register Allocator
--    Simple Register Allocator
--    Eliminate PHI nodes for register allocation
    Subregister lowering instruction pass
--    Subregister lowering instruction pass
    Live Variable Analysis
    X86 FP Stackifier
--    X86 FP Stackifier
--    Live Variable Analysis
    Prolog/Epilog Insertion & Frame Finalization
--    Prolog/Epilog Insertion & Frame Finalization
    Post RA top-down list latency scheduler (STUB)
--    Post RA top-down list latency scheduler (STUB)
    Control Flow Optimizer
--    Control Flow Optimizer
    Label Folder
--    Label Folder
    X86 AT&T-Style Assembly Printer
--    X86 AT&T-Style Assembly Printer
    Machine Code Deleter
--    Machine Code Deleter