Monday June 7, 1-2pm, 4549 Boelter Hall.

Compiler Generation and ASIP Instruction Set Design based on LISA processor models
  
Rainer Leupers
Aachen, http://www.iss.rwth-aachen.de/1_institut/dok/leupers.htm

Abstract: The efficient design of application specific instruction set
processors (ASIPs) is currently one of the major challenges in embedded SoC
design. New electronic design automation (EDA) tools are required that aid
the designer in exploring processor architectures optimized for a given
range of applications. Recently, several EDA tools have been introduced into
the market that support processor architecture exploration, including the
LISATek tool suite from CoWare Inc. that is based on the LISA 2.0
architecture description language. This talk will provide some background on
LISATek and the LISA language, and it will focus on recent and ongoing
developments in the area of C compiler generation, retargeting, and
optimization based on LISA models. While LISATek automates various stages of
architecture exploration, so far it does not support automatic synthesis or
customization of ASIP instruction sets based on application specifications.
The talk will also outline current approaches to this ASIP instruction set
synthesis problem, its position in the design flow, as well as possible
solution approaches that leverage LISATek and other existing tools.

Host: Jens Palsberg.