#
# TODO: list of fixes, refactorings, optimizations and functionality for Avrora
#

================================ F I X E S ==================================
 Comp Module Item                                      Completion (Version)
-----------------------------------------------------------------------------
    2   util  StringUtil floating point conversion
    1  input  Catch recursive include errors
    1  input  Implement fill with value .db directive
    1   devs  EEPROM read/write delays
    1  probe  Counters, branchcounters
    2  probe  getDataByte() calls from within watches
    1   devs  Frame sizes in USART implementation
    1    sim  Out of bound accesses to SRAM, flash, EEPROM
    1   devs  USART baud rates
    1   devs  USART frame sizes
    1    sim  RAMPZ usage for with more than 128k of flash

    1  input  Fixed processing of -sections option                 (1.5.118)
    1  probe  Recursion in State.getDataByte() from within watch   (1.5.102)
    2   devs  Interrupt mappings for devices on ATMega32           (1.5.102)
    1  probe  Memory monitor not reporting all of memory            (1.5.94)
    1  radio  Deadlock problems in Freespace radio                  (1.5.91)
    2  probe  BatteryMonitor hang problems                          (1.5.88)
    1  probe  TransactionalList and related probe tests             (1.5.85)
    1  probe  Various bugfixes to GDB server by Jey Kottalam        (1.5.85)
    1  radio  SimpleAir.removeRadio() does not wake remaining nodes (1.5.81)
    1    sim  Fixed RSSI livelock problem in Freespace radio        (1.5.80)
    1    sim  Fixed dynamic code update problem                     (1.5.78)
    1    sim  Remove RAMPZ accesses for ATMega32                    (1.5.70)
    1  build  Fixed errors when building with javac in 1.5          (1.5.62)
    1  probe  Fix SerialMonitor                                     (1.5.58)
    1  probe  Fix StackMonitor                                      (1.5.58)
    1   isdl  Fix negative branch offsets in disassembler           (1.5.53)
    3   isdl  Encodings for load / store instructions               (1.5.51)
    1   main  Fixed default foreground color                        (1.5.45)
    1  probe  NullPointerException inserting probe on invalid instr (1.5.43)
    1  probe  Probes inserted from within watches                   (1.5.43)
  2-3  input  Fix objdump preprocessor problems                     (1.5.xx)
    1  probe  Fixed breakpoints that were temporarily broken        (1.5.38)

======================== F U N C T I O N A L I T Y ==========================
 Comp Module Item                                      Completion (Version)
-----------------------------------------------------------------------------
  2-3  input  ELF format reader
    3   isdl  Generate assembler
    4   isdl  Generate Atmel parser
    2   isdl  Generate CFG builder
    2  probe  Introduce device instrumentation points
    2  trace  Trace monitor (state, compress output, r/w vals)
    2    gdb  Support state update in gdb monitor
    2   prof  Profile monitor (diagnos, CFG, funcs, labels)
    3     ui  Interactive simulation monitor
    1    out  Improve program dumping format
    2   devs  Implement watchdog timer
    2  radio  Implement all radio frequency registers
    1   util  Implement Columnifier class
    1   devs  IVSEL fuse support for bootloaders
    2   isdl  Better ISDL error checking
    2    sim  Unified warning system for program errors
    1  probe  Indirect call / jump monitor
    3  radio  Partial preamble loss

    1  probe  Added simplest interactive monitor                   (1.5.118)
    1    sim  Automatically patch node ID for TinyOS and SOS       (1.5.116)
    1    sim  [Bastian Schlich] ATMega16 device added              (1.5.109)
  2-3    sim  Full support for ATMega32 device                     (1.5.105)
    1   devs  Added lightsensor, RandomSensorData                  (1.5.103)
    1   devs  First version of RegisterSet for bitfields           (1.5.102)
    1  input  Fixed sections option to allow loading user sections  (1.5.94)
    2  probe  Implemented probing of interrupts                     (1.5.94)
    2  radio  Implemented probing interface for radio               (1.5.89)
    1  probe  [Simon Han] improved TripTimeMonitor                  (1.5.89)
    1 energy  [Olaf Landsiedel] ported Energy to use FSM.Probe      (1.5.88)
    2   devs  [Thomas Gaertner] implemented external flash          (1.5.88)
    2  probe  [Jey Kottalam] added probing for invalid mem accesses (1.5.85)
    2  stack  Added first version of ISE abstract interpreter       (1.5.79)
    2    sim  Added interrupt scheduling patch from John Regehr     (1.5.77)
    1    sim  Started work on ATMega32 device                       (1.5.69)
    3    sim  Support dynamic code update with SPM                  (1.5.66)
    2    sim  PinWire and PinConnection code from Jacob Everist     (1.5.57)
    2    sim  Ability to boot from locations other than 0x0000      (1.5.54)
    4   isdl  Generate Disassembler                                 (1.5.51)
    2   isdl  Generate tests for Disassembler                       (1.5.50)
    1  probe  implemented simple call / return monitor              (1.5.42)
    1  probe  implemented simple command line probing of IORegs     (1.5.40)
    2  probe  Implement probing for IO registers                    (1.5.40)
    1   sim   new: ClockDomain, refactored MCU construction         (1.5.32)
    1  probe  FiniteStateMachine, probing                            (1.5.x)
    4  probe  Implement GDB server backend                           (1.4.0)
  2-3   isdl  Constant/copy propagation optimizations                (1.4.0)
    4    sim  Dynamic Basic Block Compiler                           (1.3.x)

========================= R E F A C T O R I N G S ===========================
 Comp Module Item                                      Completion (Version)
-----------------------------------------------------------------------------
    1    sim  global migrate to Clock, DerivedClock
    2   isdl  Declare state of processor explicitly
    2   isdl  AlphaRenamer class for code processing
    2   test  Dependencies for test cases
    2   devs  ADC interface improvements
    1  radio  Radio transfer time calculation
    2  radio  Neighbor lists
    2  radio  RadioAir, distance calculations
  2-3  radio  RadioPacket refactoring, optimization
    3    sim  Implement one thread per processor model
    1   util  migrate to StringUtil.*
    1  probe  migrate to SourceMapping, remove Program.Location
    2    sim  Move sram representation to use a Segment
    2  probe  Collapse ExceptionWatch with Watch for all segments

    2    sim  Introduce Simulation class                           (1.5.104)
    2    sim  read/write vs get/set for State                      (1.5.102)
    2   devs  USART abstracted to work on multiple devices         (1.5.101)
    2    sim  Simplified and streamlined interrupt handling         (1.5.94)
  2-3  radio  Separate synch mechanism from Radio implementation    (1.5.83)
    1    sim  Renamed Radio.RadioPacket to Radio.Transmission       (1.5.76)
    2    sim  Introduced Synchronizer abstract                      (1.5.75)
    2  probe  Changed fireXXX() to accept only state and PC         (1.5.62)
    1    sim  Introduced Segment class for SRAM, flash, EEPROM      (1.5.62)
    2    sim  Introduce SourceMapping class                         (1.5.42)
    1    sim  Rename and move IOReg interface out of State          (1.5.39)
    1    sim  Move timeouts out of Simulator                        (1.5.39)
    1  input  Added help for input formats                          (1.5.38)
    1  input  Moved handling of indirect edges to ProgramReader     (1.5.38)
    2  probe  Migrate sleep probe to FiniteStateMachine.Probe       (1.5.37)
  3-4   devs  Extract ATMega128L devices                            (1.5.37)
    2   help  global migrate to HelpSystem, HelpCategories          (1.5.30)
    1   main  Remove shortName from Action, MonitorFactory          (1.5.28)
    1   main  Move class maps and defaults to Defaults               (1.5.x)
    1    sim  Refactor microcontroller instantiation                 (1.5.x)
    1  input  Check for invalid register names                       (1.5.x)
  2-3    sim  Clean up event / verbose printing                      (1.4.0)
    2   isdl  Canonicalize isdl code generated                       (1.4.0)
    1    sim  Display seconds from Simulator.Printer                 (1.4.0)
    1    sim  Synchronize simulator output                           (1.4.0)

================================ T E S T S  =================================
 Comp Module Item                                      Completion (Version)
-----------------------------------------------------------------------------
    1    sim  Event queue insert / remove / advance
    2    sim  Interrupt functionality
    1    sim  Execution timing for nontrivial programs
    3   devs  Timer0, Timer1, Timer2, Timer3 functionality
    3   devs  SPI device
    2   devs  USART devices
    2   devs  EEPROM device
    3   devs  flash update and dynamic code
    3  radio  Radio transmission timing validation
    2    sim  Probing functionality for IO registers and lower memory
    2 energy  Automated energy count tests
    2  input  Program loader and layout tests
    3   isdl  ISDL errors
    3   isdl  ISDL code manipulation and optimizations
    3   dbbc  test that simulation under DBBC is exactly as without
    2    cfg  Control flow graph construction and usage
    3  stack  Abstract value computations
    2    sim  Sleep modes
    1    sim  Probes for skip instructions (instr. size calculation)

    1    sim  First interrupt schedule testcases added             (1.5.101)
    1  probe  Fixed probe testcases to reflect transactional list   (1.5.85)
    2   isdl  Fix Disassembler testcases for relative branches      (1.5.53)

======================== O P T I M I Z A T I O N S ==========================
 Comp Module Item                                      Completion (Version)
-----------------------------------------------------------------------------
  1-2    sim  Interpreter inner loop optimization
  2-3    sim  Reduce interp. flags computations with xor's and ==
    1    sim  Optimize DerivedClock for integer multiples
  2-3   isdl  Regeneration of Instr.* classes
    1    sim  Use sram[] array directly for interp. register ops
    1    sim  Convert all clock HZ references to ints
  1-2    sim  Convert deltaqueue to use ints instead of longs
  1-2    sim  Optimize FiniteStateMachine transitions
    2    sim  Word-aligned PC optimization
    1    sim  BCLR instruction should use SREG_reg directly
    1    sim  ints instead of Register objects in Instr
    1    sim  byte-sized and short-sized immediates in Instr
    1    sim  use signed arithmetic to avoid unnecessary &'s
    1    sim  move nextPC calculation (instr body to inner loop)
    1    sim  cache relative branch targets in instr instances
    1    sim  SRAM access: subtract ioreg_end, catch AIOB exception
    2   dbbc  Register caching
    2   dbbc  Constant propagation through registers and memory
    2   dbbc  Idiom reductions
    2   dbbc  Block splitting
    3   dbbc  Register (temporary) allocation
    3   dbbc  Superblock construction
    2   dbbc  Intrablock probes and watches

    1    sim  Disabling interrupts does not terminate fast loop     (1.5.65)
    1    sim  Use shared_instr[] array directly in fast loop        (1.5.64)
    1    sim  Allocate all SPI.Frame's statically                   (1.5.35)
    1    sim  Optimize getSP() and setSP() methods                  (1.5.31)
  1-2    sim  Consolidate regs and sram in interpreter               (1.5.x)
    1    sim  ProbedInstr refactoring                                (1.5.x)
    1    sim  Move boolean xor usages to !=                          (1.4.0)

======================== D O C U M E N T A T I O N ==========================
 Comp Module Item                                      Completion (Version)
-----------------------------------------------------------------------------
    3    all  Javadoc all classes more thoroughly
    3    all  Build more complex diagrams for website
    2    all  Create TODO list available on website

    1    all  Javadoc'd most classes new since 1.4.0               (1.5.106)
