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## Package avrora.sim

Interface Summary
IORegisterConstants | The `IORegisterConstants` interface is used to centralize the numeric values of the IO registers of the AVR architecture.
Simulator.Event | The `Simulator.Event` interface represents an event that is fired when a timed event occurs within the simulator.
Simulator.Interrupt | The `Interrupt` interface represents the behavior of an interrupt (how it manipulates the state of the processor) when it is posted and when it is triggered (handler is executed by the processor).
Simulator.Probe | The `Simulator.Probe` interface represents a programmer-defined probe that can be inserted at a particular instruction in the program. or at every instruction.
Simulator.Watch | The `MemoryProbe` interface represents a user probe that is fired when a watchpoint detects an access to an address where this memory probe has been inserted.
State | The `State` class represents the state of the simulator, including the contents of registers and memory.
State.IOReg | The `IOReg` interface models the behavior of an IO register.

Class Summary
BaseInterpreter | The `BaseInterpreter` class represents a base class of the legacy interpreter and the generated interpreter(s) that stores the state of the executing program, e.g. registers and flags, etc.
Clock | The `Clock` class represents a clock within the simulation.
ClockPrescaler | The `ClockPrescaler` class represents a clock that is another clock scaled appropriately; e.g. 8x slower.
DerivedClock | The `DerivedClock` class represents a clock that is derived from another clock; i.e. the derived clock runs slower but is synchronized with the clock that it is derived from.
FIFInterpreter |
FIFInterpreter.FIFInstr |
GenInterpreter | The `GenInterpreter` class is largely generated from the instruction specification.
Simulator | The `Simulator` class implements a full processor simulator for the AVR instruction set.
Simulator.InstructionCountTimeout | The `InstructionCountTimeout` class is a probe that simply counts down and throws a `TimeoutException` when the count reaches zero.
SimulatorThread | The `SimulatorThread` class is a thread intended to run a `Simulator` in a multiple-node simulation.
State.RWIOReg | The `RWIOReg` class is an implementation of an IO register that has the simple, default behavior of being able to read and write just as a general purpose register or byte in SRAM.

Exception Summary
Simulator.BreakPointException | The `BreakPointException` is an exception that is thrown by the simulator before it executes an instruction which has a breakpoint.
Simulator.TimeoutException | The `TimeoutException` is thrown by the simulator when a timeout reaches zero.

Error Summary

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